JPH0218727B2 - - Google Patents

Info

Publication number
JPH0218727B2
JPH0218727B2 JP21363183A JP21363183A JPH0218727B2 JP H0218727 B2 JPH0218727 B2 JP H0218727B2 JP 21363183 A JP21363183 A JP 21363183A JP 21363183 A JP21363183 A JP 21363183A JP H0218727 B2 JPH0218727 B2 JP H0218727B2
Authority
JP
Japan
Prior art keywords
carry
circuit
bit
input
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP21363183A
Other languages
English (en)
Japanese (ja)
Other versions
JPS60105041A (ja
Inventor
Takeshi Shindo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP21363183A priority Critical patent/JPS60105041A/ja
Publication of JPS60105041A publication Critical patent/JPS60105041A/ja
Publication of JPH0218727B2 publication Critical patent/JPH0218727B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/506—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages
    • G06F7/508—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages using carry look-ahead circuits

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)
JP21363183A 1983-11-14 1983-11-14 加算器 Granted JPS60105041A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21363183A JPS60105041A (ja) 1983-11-14 1983-11-14 加算器

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21363183A JPS60105041A (ja) 1983-11-14 1983-11-14 加算器

Publications (2)

Publication Number Publication Date
JPS60105041A JPS60105041A (ja) 1985-06-10
JPH0218727B2 true JPH0218727B2 (en]) 1990-04-26

Family

ID=16642350

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21363183A Granted JPS60105041A (ja) 1983-11-14 1983-11-14 加算器

Country Status (1)

Country Link
JP (1) JPS60105041A (en])

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5047976A (en) * 1988-03-25 1991-09-10 Fujitsu Limited Logic circuit having carry select adders
DE68927488T2 (de) * 1988-04-20 1997-03-20 Fujitsu Ltd Binäre Übertragvorgriffsschaltung

Also Published As

Publication number Publication date
JPS60105041A (ja) 1985-06-10

Similar Documents

Publication Publication Date Title
US5151875A (en) MOS array multiplier cell
EP0827069B1 (en) Arithmetic circuit and method
US4363107A (en) Binary multiplication cell circuit
JPH0215088B2 (en])
US4471454A (en) Fast, efficient, small adder
EP0320111A2 (en) Multiple output field effect transistor logic
JPS6359171B2 (en])
US4759043A (en) CMOS binary counter
JPH0445857B2 (en])
JPS63102510A (ja) 排他的ｏｒゲートおよび／または排他的ｎｏｒゲートを構成する組合せ回路
JPH0225537B2 (en])
US4860242A (en) Precharge-type carry chained adder circuit
JP2519227B2 (ja) 桁上げ伝播速度を増加させるダイナミック論理回路を含むグル−プ段を有する並列リバイナリ加算回路
US20020188641A1 (en) Logic circuit for fast carry/borrow
US6003059A (en) Carry select adder using two level selectors
JPH0218727B2 (en])
US5812521A (en) Static adder using BICMOS emitter dot circuits
US7035893B2 (en) 4-2 Compressor
US7085796B1 (en) Dynamic adder with reduced logic
JP3137629B2 (ja) 桁上げ‐セーブ算術演算機構に対する加算器セル
EP0447254A2 (en) Array multiplier
JPS59123930A (ja) 桁上げ信号発生器
JPS63193229A (ja) 加算回路
JP3199196B2 (ja) ５入力加算器
JPH0142431B2 (en])